Power-Aware Testing and Test Strategies for Low Power Devices by Patrick Girard Nicola Nicolici & Xiaoqing Wen

Author:Patrick Girard, Nicola Nicolici & Xiaoqing Wen
Language: eng
Format: epub
Publisher: Springer US, Boston, MA

6.2.3 Test Scheduling

For a given modular SOCs where cores are wrapped such that each core is a testable unit, and an infrastructure for test data transportation, a so-called TAM, exists, the test scheduling is the process of planning the order in which the cores are to be tested. The scan chains at each testable unit are formed into wrapper chains, and given the test patterns, each testable unit is associated with a test time. The objective of test planning is to plan the test application such that the overall test cost, which often is related to test application time, is minimal.

A number of approaches have been proposed for test scheduling. For IC with blocks-of-logic, testable units, that can be scheduled independently, Abadir and Breuer (1986) and Craig et al. (1988) have proposed techniques. Early work on test scheduling for modular designs was performed by Larsson and Peng (1999, 2000) and Chakrabarty (2000). And substantial work has been performed on integrated wrapper design, TAM design, and test scheduling. For example, by Iyengar et al. (2001), Yoneda and Fujiwara (2002), Yoneda et al. (2006), Goel and Marinissen (2003), Su and Wu (2004), and Larsson and Peng (2002a). Koranne (2002) proposed a test scheduling algorithm assuming reconfigurable core wrappers, and Larsson and Fujiwara (2006) showed it is possible to define an optimal test scheduling approach based on re-configurable core wrappers when making use of preemptive scheduling.

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